1. Field of the Invention
This invention relates generally to a semiconductor device and a process for fabricating the device. More specifically, the present invention relates to a MOS field effect transistor which includes a non-uniformly doped well region.
2. Description of the Related Art
As integration of semiconductor devices advances toward higher density, miniaturization of the devices continues. Although metal-oxide-semiconductor (MOS) field effect transistors are generally advantageous for the integration, there have arisen problems such as, for example, an increasing current leakage due to short channel effects as the miniaturization progresses.
Problems are caused by a widened depletion region and from increased normal electric field due to higher impurity concentration in a channel region.
In an attempt to obviate the above problems, there have been reported two transistor structures, in which, generally, a non-uniformly doped channel is formed on a semiconductor substrate. These two structures will be described herein below.
One structure is described as an NUDC (non-uniformly doped channel) structure by Okamura et al., Technical Digest of International Electron Devices Meeting, December 1990, page 391. This structure is composed of two channel portions in a well region, each having different net impurity concentrations.
A method for fabricating a field effect semiconductor with an NUDC structure has been disclosed in Japanese Laid-Open Patent Application No. 5-129326, to suppress short channel effects, increase a source or drain junction breakdown voltage and improve high frequency characteristics of the transistor.
According to the disclosure, and as shown in FIG. 5, a channel region between source and drain regions 19 in a semiconductor substrate 12, is composed of two portions. A first portion 16 is situated partially under a gate electrode 13 via insulating layer 14 and is contiguous to the source and drain junction regions, and has a low net impurity concentration. The other portion 11 is the remainder of the well, and has a high concentration of impurities of a conductive type opposite to that of the semiconductor substrate 12. The device also includes sidewalls 18, portions 17 and isolation layers 15.
The formation of the above-mentioned channel region is carried out by (1) forming a well region having a high impurity concentration by implanting first conductive type ions, and (2) subsequently forming the low net impurity concentration portion in the vicinity of the above-mentioned junction regions by counter doping, that is, by implanting ions having a second conductive type opposite to that of the first type, to compensate for some of the previously implanted first conductive type ions.
In the above-mentioned semiconductor device, however, a threshold voltage can not be sufficiently decreased To because the structure has a high impurity concentration region continuously disposed from a surface region between the source and drain regions under the gate electrode to inner portions of the well in contact with a semiconductor substrate.
The other semiconductor structure which has been disclosed in an attempt to obviate or minimize the aforementioned problems is described in Japanese Laid-Open Patent Application No. 6-112478.
According to the disclosure, a high impurity concentration layer of the same conductivity type as that of the substrate is formed in a channel part through an ion implantation method. Ions of a conductivity type opposite to that of the substrate are implanted to lessen the high impurity concentration layer of the channel part in impurity concentration near a diffusion layer. The high impurity concentration layer of the same conductivity type as that of the substrate 11 is located only near the center of the channel and lessened in impurity concentration near the source d rain diffusion layers.
However, a channel between the source and drain regions in this structure is implanted with ions having the same conductive type as that of the well region during the above channel implantation. Although some improvement in the punch-through effect may be achieved by this implantation, low voltage driving characteristics have not be en fulfilled for this structure.
It is noted that the depth profile of impurity concentration produced in a well region by high energy ion implantation is, in general, considerably different from that produced by a thermal diffusion process. Namely, the former produces a concentration profile such that an impurity concentration at the surface region is appreciably different from that inside the substrate, while the latter produces a profile relatively uniform with the depth from the surface of the semiconductor substrate.
To fabricate a MOS field effect transistor which is capable of operating at higher frequencies, it is necessary for a well region of the transistor to have (1) a low impurity concentration to decrease its source or drain junction capacitance, and (2) a high impurity concentration to increase its well junction breakdown voltage and thereby decrease the design rule for the transistor. In other words, as an ideal field effect transistor which is able to satisfy the requirements mentioned just above, a transistor preferably has a structure in which the well region as a whole has a high impurity concentration, while the junction regions of the source and drain regions have low impurity concentrations.